1. Field of the Invention
This invention relates generally to bipolar transistors, and relates more particularly to a walled-emitter, polysilicon-contact, bipolar transistor having improved base characteristics, and a method for fabricating such a transistor.
2. Description of the Relevant Art
A walled-emitter, bipolar transistor has an emitter and active base that extend to an isolation oxide at one or more places. FIG. 1 depicts a plan view of a vertical, walled-emitter, bipolar transistor 10. The dashed lines 12 define boundaries between the doped regions of the transistor 10 and a surrounding isolation oxide 14. A collector contact 16, a base contact 18, and an emitter contact 20 form electrical connections with the collector, base, and emitter, respectively, of the transistor. The emitter of transistor 10 is in the doped region below the emitter contact 20. The emitter extends to the isolation oxide 14 at two locations 22 and 24. The active base of transistor 10 is below the emitter region and also extends to the isolation oxide 14 at locations 22 and 24. One advantage of walled-emitter transistor design is that it makes effective use of the active base area while minimizing the parasitic collector-base capacitance for a given emitter area.
Connections or contacts to the doped regions of a bipolar transistor can be made with polysilicon, which effectively adds one level of interconnection among devices. Polysilicon contacts for bipolar transistors are common for integrated circuits having both bipolar and MOS (or CMOS) devices on the same chip.
A process for fabricating polysilicon-contact, bipolar NPN transistors typically includes the following steps. After n+ buried layers and an epitaxial layer are formed on the substrate, isolation oxide is formed to isolate regions of the substrate into n-type wells for separate transistors. Then, a layer of polysilicon is deposited on top of the substrate. The polysilicon is implanted with a p-type dopant, like boron, and diffused into the substrate to form the base of a bipolar transistor. Then, portions of the substrate are masked and the polysilicon is implanted with an n-type dopant, like arsenic, to form the emitter and emitter contacts of the bipolar transistor. The substrate is masked again and the polysilicon is implanted with a p-type dopant to form the base contacts of the transistor. During this last step, the emitter region is masked so that the p-type dopants do not enter the emitter region. After implantation, the substrate is annealed to diffuse the dopants into the silicon substrate. The three implantation steps described above may be referred to as a base implant, an n+ polysilicon implant, and a p+ polysilicon implant, respectively. The order of the n+ and p+ polysilicon implant steps is interchangeable.
One constraint to fabricating high performance, polysilicon-contact transistors with walled-emitters is the effect that device isolation can have on key parameters like leakage current (Iceo) and breakdown voltage (BVceo). As shown in FIG. 2, the problem is that a typical walled-emitter transistor has an active base region 26 that is thinner at the isolation edges 22 and 24. Note that the emitter region 28 extends to the isolation oxide 14, making it a "walled-emitter" at locations 22 and 24. Also shown in FIG. 2 are a buried layer 30 and a substrate 32. The buried layer 30 is part of the collector region of the transistor 10.
The active base 26 is thinner at the isolation edges 22 and 24 because the base implantation is less effective at those locations. When the base is formed during the base implant, an angled edge or "bird's beak" of the isolation oxide overlaps and shields the edge of the base. During the base implant, the bird's beak absorbs some of the implanted atoms, so that fewer dopant atoms are implanted at the edge of the base. Also, some of the base dopant atoms that are implanted at the edges of the base will diffuse laterally from the base into the oxide during subsequent annealing steps. The combined result of shielding by the oxide bird's beak and lateral diffusion into the oxide is that the active base 26 is thinner at the isolation edges 22 and 24 that it is away from the edges.
The thinner base 26 at the isolation edges 22 and 24 provides a site for current leakage between the emitter 28 and collector 30 and also decreases breakdown voltage. Breakdown voltage can be so low that the transistor cannot operate at maximum supply voltages. Vertical scaling of such a transistor is severely constrained, compromising device parameters such as beta and unity gain cutoff frequency, which are determined by base thickness.
One approach to overcoming the above-described problem is to laterally extend the oxide well region and open up a gap between the oxide and the edge of the emitter region. Such a transistor is not a "walled-emitter" transistor because the emitter does not extend to the oxide wall. The transistor would have an active base under the emitter of relatively uniform thickness, unaffected by the edge of the isolation oxide. A disadvantage of this approach is that more surface area is needed to fabricate a transistor having comparable performance to that of a wall-emitter transistor.